With rapid development of hardware in recent years, existing services can no longer make full use of resources. Consequently, resource utilization is low, and return on investment of an enterprise cannot be maximized. In order to improve the resource utilization, at present, a shared input/output (shared IO) technology is put forward in the industry. That is, a single-root input/output virtualization (SR-IOV) device can be shared among different peripheral component interconnect express (PCIe) domains (that is, among different physical machines), and a physical sub-device (such as physical function (PF)) or virtual sub-device (such as virtual function (VF)) of the SR-IOV device may be bound to different hosts, and is used in a same way as a normal PCIe device. In a shared IO architecture, a global PCIe domain needs to be maintained by management central processing units (mCPU) in order to improve system reliability, a primary mCPU and a secondary mCPU are usually set among mCPUs for active/standby redundancy. When the primary mCPU breaks down, failover is performed between the primary mCPU and the secondary mCPU, that is, the secondary mCPU serves as a primary mCPU to continue to process a host service.
However, when the secondary mCPU performs failover processing, the secondary mCPU usually needs to enumerate each PCIe device again, which results in an interruption of a host service during the failover. Moreover, a more serious problem may arise: the primary mCPU is responsible for accessing a PCIe device according to a request for accessing the PCIe device sent by a host and returning an access response to the host. If the primary mCPU breaks down and failover to the secondary mCPU cannot be performed quickly in time, the access request of the host cannot be processed in time, which may lead to a breakdown of the host because of an access timeout, and may also lead to breakdowns of all hosts in an entire PCIe network for the same reason, thereby reducing reliability of the PCIe network.